FIGS. 1 and 2 show an example of a resistor produced in an integrated circuit, FIG. 2 shows a view from above of FIG. 1 generally in a plane II-II and FIG. 1 shows a cross-sectional view through FIG. 2 in a plane I-I.
In this example, the resistor is formed in a semiconductor well PW that is of the triple-well type, i.e. the well PW is isolated from a semiconductor substrate PSUB by an isolating layer NISO and isolating regions NW.
The two terminals P1, P2 of the resistor are formed by highly doped P+ contact zones located on the surface of the well PW (i.e. level with a front face of said well). The contact zones are electrically isolated from each other by the conventional means of an insulating shallow trench isolation STI. The shallow trench isolation STI, which covers most of the surface of the well PW, has deliberately not been shown in FIG. 2 for the sake of clarity.
Thus, a resistive region through which a current may flow, for example when a voltage is applied across the terminals P1 and P2, is formed by the material forming the well PW having a given resistivity (in particular dependent on the density of implanted dopant), with that region of the well PW electrically connecting the terminals P1 and P2. The region of the well PW forming the resistive region is, in particular, located between the shallow trench isolation STI and the buried layer NISO.
FIG. 3 shows another example of a resistor of an integrated circuit, in which two terminals P1 and P2 are electrically connected by a conductive track PCR. This type of embodiment is generally formed on the surface of a substrate or of a semiconductor well or indeed in the interconnect levels of the integrated circuit.
The conductive track PCR is made from a conductor having a resistivity chosen depending on the requirements, for example silicided N+ polysilicon, N+ polysilicon, P+ polysilicon, P+ silicon, or a metal.
The conductive track PCR having a given resistivity also forms a resistive region through which a current may flow, for example when a voltage is applied across the terminals P1 and P2.
In these two example resistors, the resistance R of the resistor may be expressed by the approximation R=ρ*L/S, where ρ is the resistivity of the material of the resistive region, L is the length of the resistive region (i.e. the distance travelled in the resistive region to get between the terminals P1 and P2), and S is the area of a cross section of the resistive region.
Configuring the metal tracks PCR so that they have a sinuous shape, i.e. what is called a “serpentine”, as shown in FIG. 3, allows the length L of the resistive region to be increased while limiting the substrate area occupied between the two terminals P1 and P2. The resistance R of the resistor may be modified between various embodiments by varying the length L.
However, in embodiments of the type of the preceding examples, it is difficult to control the area S of the cross section of the resistive region, for example because of constraints on production of the conductive tracks PCR, or, as FIG. 2 shows, because the “width” D of the cross section of the resistive region is not very controllable and cannot be considerably decreased because of constraints on the formation, often by lithography or implantation, of the regions NW defining the edges of said resistive region.
Furthermore, it is desirable to minimize the space occupied in and on the substrate or semiconductor well by the components of an integrated circuit.